幻境 | 技术笔记

如何在Verilog testbench中实现随机数

您在此:
预计阅读时间 少于1分钟

问题现象
因为Verilog $random并不能指定初始化种子,所以导致每次生成的随机状态一致

解决方案
引入系统时钟,并且使用
integer FP;
integer fgetsResult;
integer sscanfResult;
integer NowInSeconds;
reg [8*10:1] str;

$system(“date +%s > now_in_seconds”);
FP = $fopen(“now_in_seconds”,”r”) //Get random seed

// get a string from the open file – “fgetsResult” should be a 1 – you can test
// that for completeness if you’d like
fgetsResult = $fgets(str,FP)

// convert the string to an integer – “sscanfResult” should also be a 1, and
// you can test that, too,
sscanfResult = $sscanf(str,”%d”,NowInSeconds

$fclose(FP); // closes the file
process::self.srandom(NowInSeconds);

这篇文章有用吗?
踩爆 0
已阅读次数: 395